Article
An Integrated Method for Transistor-to-Gate Level Performance Degradation Analysis
In this research, an integrated method to analyse the degradation of performance in digital circuit is brought out through the transistor level to the gate level. To accurately predict circuit behaviour with time, by incorporating both gate-level analysis of timing with device-level ageing models the proposed methodology provides a framework to achieve this. The method also includes process variation, bias temperature instability (BTI) and hot carrier injection (HCI) effects to enable comprehensive deterioration monitoring over base cell libraries. The combination of gate-level timing models and SPICE-level degradation data can be used to efficiently and correctly identify the aging-related design issues by using the hybrid-simulation-based design evaluation. Experiments on benchmark circuits yield improvement in the accuracy of the forecast, as well as aging-prone key paths. This approach is enhanced in sophisticated semiconductor technology to ensure design optimisation that ensures long term reliability.
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