Suresh Yadav 01 04 In this research an integrated method to analyse the degradation of performance in digital circuit isbrought out through the transistor level to the gate level To accurately predict circuit behaviour with time byincorporating both gatelevel analysis of timing with devicelevel ageing models the proposed methodology providesa framework to achieve this The method also includes process variation bias temperature instability BTI and hotcarrier injection HCI effects to enable comprehensive deterioration monitoring over base cell libraries Thecombination of gatelevel timing models and SPICElevel degradation data can be used to efficiently and correctlyidentify the agingrelated design issues by using the hybridsimulationbased design evaluation Experiments onbenchmark circuits yield improvement in the accuracy of the forecast as well as agingprone key paths This approachis enhanced in sophisticated semiconductor technology to ensure design optimisation that ensures long termreliability Copyright (c) Journal of Engineering Technology and Sciences. All rights reserved 2026